The present invention generally relates to a CMOS process and more specifically to a method of fabricating a high voltage self-aligned MOS transistor in a low voltage CMOS process, and to a semiconductor structure comprising such a high voltage self-aligned MOS transistor integrated with low voltage CMOS components.
In modern low voltage CMOS processes the line widths, distances and layer thicknesses are more and more reduced in order to increase the speed and decrease the size of the components in the CMOS circuit.
As a result of this also feed voltages and signal voltages are reduced. For digital components this is a benefit since it saves electrical power. In analog applications, such as e.g. mixed signal and radio frequency (RF) applications, however, a voltage dynamics may be needed which is not possible to obtain using such a low voltage CMOS process.
If additional process steps were added to a conventional low voltage CMOS process, it would be possible to fabricate low voltage and high voltage transistors on the same chip in a BiCMOS process, but such process would be more complicated and thus more costly compared to conventional CMOS manufacturing technology.
Another solution would be to employ a dual gate CMOS process, which includes the fabrication of CMOS devices with two different gate oxides. A component having a thicker gate oxide would be able to handle the higher voltage. Such process is also more complicated and furthermore, it may be difficult to achieve sufficiently good performance e.g. in radio frequency applications using such kind of MOS devices because such thicker gate oxide deteriorates the performance at high frequency.
Still a further way to incorporate fabrication of high voltage components into a low voltage CMOS process is described in H. Ballan et al. xe2x80x9cHigh voltage devices and circuits in standard CMOS technologiesxe2x80x9d, Kluwer Academic Publishers, 1999, pages 78-79, and uses a LOCOS oxide inside the high voltage component to increase its breakdown voltage. The channel area and its length are defined before the depositing and etching of the polysilicon. A drawback of such an approach is that the channel is not self-aligned.
Further, lateral self-aligned DMOS structures have been integrated in the CMOS process flow but the channel area has been diffused from the edge of e.g. the gate structure. Such a provision needs an additional annealing step, which may not always be desirable since the thermal budget in many processes is very limited. Furthermore, an optimal doping gradient in the channel area is not obtained since the highest channel doping is automatically obtained closest to the source area.
U.S. Pat. No. 5,891,782 issued to S. T. Hsu et al. and WO95/26045 (A. Sxc3x6derbxc3xa4rg et al.) disclose methods for forming channel areas by means of an inclined implantation. However, the resulting structures are not capable of allowing high voltages to be applied between the drain and the gate and such limitation is not acceptable in many applications. Further, the designs are very dependent on how the transistor structures are oriented on the substrate, which further complicates the fabrication processes.
It is consequently an object of the present invention to provide, in a CMOS process, a method for forming a high voltage MOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, while overcoming at least some of the problems associated with the prior art.
It is a further object of the present invention to provide such method which is capable of fabricating a high voltage MOS transistor which possesses very good performance as regards e.g. breakthrough voltages and noise levels.
It is still a further object of the invention to provide such method which is capable of fabricating integrated circuits for digital and analog radio frequency (RF) applications.
It is yet a further object of the invention to provide such method which is easy to perform and which provides for high fabrication yields.
It is in this respect a particular object of the invention to provide such method that adds a minimum of additional process steps to a conventional low voltage CMOS process.
These objects among others are, according to one aspect of the invention, fulfilled by a method wherein a semiconductor substrate is provided; n-well regions for the high voltage NMOS transistor and the low voltage PMOS transistor are formed in the substrate by means of ion implantation; a p-well region for the low voltage NMOS transistor is formed in the substrate by means of ion implantation; and isolation areas are formed on top of and/or in the substrate to laterally separate the transistor from each other and to define a voltage distributing region in the high voltage NMOS transistor. The isolation areas are typically LOCOS or shallow trench isolation (STI). Further gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, are produced by forming a respective thin gate oxide on the substrate; depositing a conducting or semiconducting layer thereon; and patterning said layer to form the respective gate regions. The gate region for the high voltage NMOS transistor is here formed partly above the isolation area defining the voltage distributing region.
Subsequently thereto, a p-doped channel region for the high voltage NMOS transistor is formed in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region. According to the present invention this p-doped channel region is formed by ion implantation through a mask, where the ion implantation is effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the channel region partly underneath the gate region of the high voltage NMOS transistor.
Finally, drain and source regions for the low voltage PMOS transistor are formed by means of creating ion implanted p+-regions; and drain and source regions for the high voltage and low voltage NMOS transistors are formed by means of creating ion implanted n+ regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region.
According to a further aspect of the invention a corresponding method for forming a high voltage PMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor on a chip is provided.
According to yet a further aspect of the invention a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor in a MOS process (e.g. CMOS, BiCMOS, or NMOS process) comprising the steps of providing a semiconductor substrate; forming n-well regions for the high voltage NMOS transistor in the substrate by means of ion implantation; forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation; forming isolation areas on top of and/or in the substrate to laterally separate the transistors from each other and to define a voltage distributing region in the high voltage NMOS transistor; producing gate regions for the high voltage NMOS transistor and the low voltage NMOS transistors, respectively, by forming a respective thin gate oxide on the substrate; depositing a layer of a conducting or semiconducting material thereon; and patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region; forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region; and forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n+ regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region. According to the invention, the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor.
An advantage of the present invention is that improved high voltage and low voltage components can be integrated into a single MOS process through the sole adding of a mask step and an ion implantation step.
Further, the channel length is very well defined by forming the channel region by means of ion implantation only.
By performing the inclined implantation in a plurality of different directions, e.g. four, the orientation of the high voltage NMOS transistor on the chip is not crucial.
Further advantages and characteristics of the present invention will be disclosed in the following detailed description of embodiments.